Architecture

diagram

The machine has 16 general-purpose registers with numbers from 0 to F.
Each register has a width of one Byte.
Any distinct register within the instructions is referenced by 4 Bits. (0000 corresponds to register 0, 0100 to register 4, 1111 to register F ...)
The machine utilizes a Main Memory of 256 Bytes.
Each memory cell (one Byte) is accessed using an address ranging from 0 to 255(00 to FF hexadecimal).
Floating-point values are represented as followed: (from most significant bit downwards): 1 Bit prefix (+/-), 3 Bit Exponent, 4 Bit Mantissa.
Each machine instruction has a length of 2 Byte and consists of an Op-Code with 4 Bit and an operand-field of 12 Bits.
The following description uses the letters R, S, T within the operand for a hexadecimal number, which points to the number of a register.
The letters X and Y within the operand point to hexadecimal numbers, which do not represent registers. These represent a hexadecimal value or an address in the memory between 00 and FF.

Opcodes

Opcode Operand Description
1 RXY LOAD register R with data from memory cell with address XY.
2 RXY LOAD register R with value of (Bit-pattern) XY.
3 RXY STORE data from register R in memory cell with address XY.
4 0RS MOVE data from register R to register S.
5 RST ADD data from register S and register T (Two Complement Interpretation), saving the result to register R.
6 RST ADD data from register S and register T (Floating-Point Interpretation), saving the result to register R.
7 RST OR of Bit pattern from register S and register T, saving the result to register R.
8 RST AND of Bit pattern from register S and register T, saving the result to register R.
9 RST XOR of Bit pattern from register S and register T, saving the result to register R.
A R0X ROTATE the Bit pattern in register R one Bit to the right, X-times.
B RXY JUMP to instruction in memory cell with the address XY, if the data in register R is equal to the data in register 0.
C 000 HALT.
Extended Set for Vizmachine
D XYZ WAIT in milliseconds defined by XYZhex value.
E RST WRITE data from register R in memory cell with address given in register T.

Machine

 Settings
   

PROGRAM COUNTER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTER
R{{$index.toString(16).toUpperCase()}}
MAIN MEMORY
  
0{{$index.toString(16).toUpperCase()}}
{{$index.toString(16).toUpperCase()}}0
Legend: Program Counter Program Cells Cells with Data Empty Cells
COMMAND LOG     
Address Command Data Description

Program in Assembler

Program Size: {{(vctrl.vcommands.length==0)?0:(vctrl.vcommands.length-1)*2}} Bytes
Reset Memory

Set Starting Point in Memory: 
Address	 Opcode	Operand	Description
{{cmd.address.substr(0,2)}}|{{cmd.address.substr(2)}}			{{vctrl.getCommandDescription(cmd.command.codeDec,cmd.opcode.substr(1))}}

Screens

Display (2x16)

Last 16 addresses of memory wil be displayed as ASCII.

{{vctrl.getASCII(224+n)}}

{{vctrl.getNumber(224+n)}}

{{vctrl.getASCII(240+n)}}

{{vctrl.getNumber(240+n)}}

Memory Usage

Memory is displayed in grey-scale blocks.

CELL NUMBER #{{vctrl.screencellnumber}}

Downloads

Vizmachine

Manual (en, de) in PDF

Exercises

Exercises (en, de) in PDF
Solutions for 1, 2a, 2b, 3, 4a, 4b as *.vzm dumps.
Further exercises using this virtual machine (en, de)

Demos

Demo for JUMP and WAIT as *.vzm dump. (Run program and look at memory usage screen!)

About


VizMachineV{{vctrl.version}}

GNU AFFERO GENERAL PUBLIC LICENSE
Version 3, 19 November 2007
LICENSE.txt

A-Knoll-EDGED

Copyright (C) 2003-2015 by Mathias Knoll
Program: DI(FH) Mathias Knoll, MSc Mail: mathias.knoll-AT-fh-joanneum.at
Learning Material / Refining: DI Manfred Pamsl Mail: manfred.pamsl-AT-fh-joanneum.at
Architecture Idea from "Computer Science: An Overview (12th Edition)" by Glenn Brookshear & Dennis Brylow

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E-Mail: itm@fh-joanneum.at